搜索资源列表
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
LAC_adder16
- 十六位超前进位加法器，Verilog HDL-16-ahead adder, Verilog HDL
verilog.HDL.examples
- 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
adder_Xilinx_Spartan_3
- 这是个基于 Xilinx Spartan3 的加法器，利用Verilog语言编写，对于EDA初学者来说有一定的参考价值。 -This is based on the Xilinx Spartan3 Adder, Verilog language use, EDA newcomer has some reference value.
FullAdder
- This a code programed in Verilog Language. It is Full Adder code designed using Half Adder-This is a code programed in Verilog Language. It is Full Adder code designed using Half Adder..
fpufiles
- floating point adder mul and sub in verilog code
16bit-CLA
- a 16 bit carry look ahead adder verilog code
adder
- actel fpga加法器的verilog源码，在libero环境开发的-actel fpga adder verilog source code, development environment in the libero
a-floating-point-adder
- 一个浮点加法器，verilog描述，数据格式：高14位为尾数，低四位位指数（带符号数运算）-A floating point adder Verilog descr iption
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
Verilog Full Adder
- This is some real adder type stuff. To the fullest degree.
pararel-8-bit-adder-verilog
- implementation of 8bit adder with pararel computation. It s use S/P converter and P/S converter. The code is written in verilog language
Adder
- 本代码为用三种方法实现verilog加法器代码，在ISE中基于Spartan6仿真成功。-This code is used three methods to achieve adder verilog code, based on the success in the ISE Spartan6 simulation.
Carry-Skip Adder
- 经典的进位跳跃、进位选择、并行前缀加法器，16位，基于verilog HDL语言(16-bit carry-skip adder)
Lab1_Skeleton.tar
- adder verilog lab 1 assignment
verilog四则运算器
- verilog四则运算，包括加法器、乘法器、除法器，不过都是拾人牙慧，整理一下，供新手参考。(Verilog four operations, including the adder, multiplier and divider, but are written, tidy, for novice reference.)
verilog add4
- 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)
Verilog codes
- IT IS A CARRY S ELECT ADDER TO IMPROVE PERFORMANCE.
Fixed-Floating-Point-Adder-Multiplier-master
- Fixed-Floating-Point-Adder-Multiplier with test bench
adder
- 实现了加法器功能，包含testbench(Implements the adder function)